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ltc2285 1 2285fb typical application features applications description dual 14-bit, 125msps low power 3v adc the ltc ? 2285 is a 14-bit 125msps, low power dual 3v a/d converter designed for digitizing high frequency, wide dynamic range signals. the ltc2285 is perfect for demanding imaging and communications applications with ac performance that includes 72.2db snr and 82db sfdr for signals at the nyquist frequency. typical dc specs include 1.5lsb inl, 0.6lsb dnl. the transition noise is a low 1.3lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.6v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. a data ready output clock (clkout) can be used to latch the output data. snr vs input frequency, C1db, 2v range n integrated dual 14-bit adcs n sample rate: 125msps n single 3v supply (2.85v to 3.4v) n low power: 790mw n 72.4db snr, 88db sfdr n 110db channel isolation at 100mhz n flexible input: 1v p-p to 2v p-p range n 640mhz full power bandwidth s/h n clock duty cycle stabilizer n shutdown and nap modes n data ready output clock n pin compatible family 125msps: ltc2283 (12-bit), ltc2285 (14-bit) 105msps: ltc2282 (12-bit), ltc2284 (14-bit) 80msps: ltc2294 (12-bit), ltc2299 (14-bit) 65msps: ltc2293 (12-bit), ltc2298 (14-bit) 40msps: ltc2292 (12-bit), ltc2297 (14-bit) n 64-pin (9mm 9mm) qfn package n wireless and wired broadband communication n imaging systems n spectral analysis n portable instrumentation l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. C + input s/h analog input a analog input b clk a clk b 14-bit pipelined adc core clock/duty cycle control output drivers ? ? ? ov dd ognd mux clkout d13a d0a ? ? ? ov dd ognd 2285 ta01 d13b d0b C + output drivers input s/h 14-bit pipelined adc core clock/duty cycle control of input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 75 72 100 200 250 2285 ta01b 67 73 74 71 50 150 300 350
ltc2285 2 2285fb pin configuration absolute maximum ratings supply voltage (v dd ) ..................................................4v digital output ground voltage (ognd) ........ ?0.3v to 1v analog input voltage (note 3) .......?0.3v to (v dd + 0.3v) digital input voltage ......................?0.3v to (v dd + 0.3v) digital output voltage ................ ?0.3v to (ov dd + 0.3v) power dissipation .............................................1500mw operating temperature range ltc2285c ................................................ 0c to 70c ltc2285i.............................................. ?40c to 85c storage temperature range ................... ?65c to 150c ov dd = v dd (notes 1, 2) top view 65 up package 64-lead (9mm 9mm) plastic qfn t jmax = 150c, oea o a a a a a a o o eeb b b oeb b b b b b b b o o orerorao earee aearee arar aaeero eerarerae b rb b rb eabae aearee arar aaeero eerarerae r r araeer oo a r
ltc2285 3 2285fb analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + Ca in C ) 2.85v < v dd < 3.4v (note 7) 0.5v to 1v v v in,cm analog input common mode (a in + +a in C )/2 differential input drive (note 7) single ended input drive (note 7) 1 0.5 1.5 1.5 1.9 2 v v i in analog input leakage current 0v < a in + , a in C < v dd C1 1 a i sense sensea, senseb input leakage 0v < sensea, senseb < 1v C3 3 a i mode mode input leakage current 0v < mode < v dd C3 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 640 mhz dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 72.4 db 30mhz input 72.3 db 70mhz input 68.9 72.2 db 140mhz input 71.7 db sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 88 db 30mhz input 85 db 70mhz input 70 82 db 140mhz input 78 db sfdr spurious free dynamic range 4th harmonic or higher 5mhz input 90 db 30mhz input 90 db 70mhz input 77 90 db 140mhz input 90 db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 72.2 db 30mhz input 72 db 70mhz input 67 71.9 db 140mhz input 70.2 db i md intermodulation distortion f in = 40mhz, 41mhz 85 db crosstalk f in = 100mhz C110 db the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) converter characteristics parameter conditions min typ max units gain matching external reference 0.3 %fs offset matching 2 mv transition noise sense = 1v 1.3 lsb rms
ltc2285 4 2285fb internal reference characteristics (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/c v cm line regulation 2.85v < v dd < 3.4v 3 mv/v v cm output resistance | i out | < 1ma 4 digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units logic inputs (clk, oe , shdn, mux) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd C10 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a 2.7 2.995 2.99 v v v ol low level output voltage i o = 10a i o = 1.6ma 0.005 0.09 0.4 v v ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v
ltc2285 5 2285fb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 8) power requirements symbol parameter conditions min typ max units v dd analog supply voltage (note 9) 2.85 3 3.4 v ov dd output supply voltage (note 9) 0.5 3 3.6 v iv dd supply current both adcs at f s(max) 263 305 ma p diss power dissipation both adcs at f s(max) 790 915 mw p shdn shutdown power (each channel) shdn = h, oe = h, no clk 2 mw p nap nap mode power (each channel) shdn = h, oe = l, no clk 15 mw the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) timing characteristics symbol parameter conditions min typ max units f s sampling frequency (note 9) 1 125 mhz t l clk low time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 3.8 3 4 4 500 500 ns ns t h clk high time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 3.8 3 4 4 500 500 ns ns t ap sample-and-hold aperture delay 0 ns t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns t c clk to clkout delay c l = 5pf (note 7) 1.4 2.7 5.4 ns data to clkout skew (t d C t c ) (note 7) C0.6 0 0.6 ns t md mux to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 7) 4.3 10 ns bus relinquish time (note 7) 3.3 8.5 ns pipeline latency 5 cycles note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 125mhz, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code ? ickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 125mhz, input range = 1v p-p with differential drive. the supply current and power dissipation are the sum total for both channels with both channels active. note 9: recommended operating conditions.
ltc2285 6 2285fb typical performance characteristics crosstalk vs input frequency typical inl, 2v range, 125msps typical dnl, 2v range, 125msps 8192 point fft, f in = 5mhz, C1db, 2v range, 125msps 8192 point fft, f in = 30mhz, C1db, 2v range, 125msps 8192 point fft, f in = 70mhz, C1db, 2v range, 125msps 8192 point fft, f in = 140mhz, C1db, 2v range, 125msps 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, C1db, 2v range, 125msps grounded input histogram, 125msps input frequency (mhz) 0 C130 crosstalk (db) C125 C120 C115 C110 C105 C100 20 40 60 80 2285 g01 100 code 0 inl error (lsb) 12288 2285 g02 4096 8192 16384 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 code 0 dnl error (lsb) 12288 2285 g03 4096 8192 16384 1.0 C1.0 0.8 C0.8 0.6 C0.6 0.4 C0.4 0.2 C0.2 0 frequency (mhz) 0 amplitude (db) 2285 g04 10 20 30 40 50 60 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2285 g05 10 20 30 40 50 60 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2285 g06 10 20 30 40 50 60 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2285 g07 10 20 30 40 50 60 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2285 g08 10 20 30 40 50 60 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 code 8183 8185 8187 8189 8191 8193 31 54 68 581 637 count 12000 16000 20000 2285 g09 8000 4000 10000 14000 18000 6000 2000 0 3380 3316 11299 10516 17646 18027
ltc2285 7 2285fb typical performance characteristics snr vs input frequency, C1db, 2v range, 125msps sfdr vs input frequency, C1db, 2v range, 125msps snr and sfdr vs sample rate, 2v range, f in = 5mhz, C1db snr vs input level, f in = 70mhz, 2v range, 125msps sfdr vs input level, f in = 70mhz, 2v range, 125msps i vdd vs sample rate, 5mhz sine wave input, C1db i ovdd vs sample rate, 5mhz sine wave input, C1db, 0v dd = 1.8v snr vs sense, f in = 5mhz, C1db input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 75 72 100 200 250 2285 g10 67 73 74 71 50 150 300 350 input frequency (mhz) 0 85 90 100 150 250 2285 g11 80 75 50 100 200 300 350 70 65 95 sfdr (dbrs) sample rate (msps) 0 50 snr and sfdr (dbfs) 60 70 80 90 20 40 60 80 2285 g12 100 120 140 160 sfdr snr input level (dbfs) C70 snr (dbc and dbfs) 70 C40 2285 g13 40 20 C60 C50 C30 10 0 80 dbfs dbc 60 50 30 C20 C10 0 input level (dbfs) C80 sfdr (dbc and dbfs) 60 90 100 0 2285 g14 50 40 0 C60 C40 C20 C70 C50 C30 C10 20 110 dbfs dbc 80 70 30 10 sample rate (msps) 0 i vdd (ma) 260 280 80 2285 g15 240 220 250 270 290 230 210 200 190 20 40 60 100 120 140 2v range 1v range sample rate (msps) 0 i ovdd (ma) 14 60 2285 g16 8 4 20 40 80 2 0 16 12 10 6 100 120 140 sense pin (v) 0.4 64 snr (dbfs) 65 67 68 69 74 71 0.6 0.8 0.9 2285 g17 66 72 73 70 0.5 0.7 1.0 1.1
ltc2285 8 2285fb pin functions a ina + (pin 1): channel a positive differential analog input. a ina C (pin 2): channel a negative differential analog input. refha (pins 3, 4): channel a high reference. short to- gether and bypass to pins 5, 6 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. refla (pins 5, 6): channel a low reference. short to- gether and bypass to pins 3, 4 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. v dd (pins 7, 10, 18, 63): analog 3v supply. bypass to gnd with 0.1f ceramic chip capacitors. clka (pin 8): channel a clock input. the input sample starts on the positive edge. clkb (pin 9): channel b clock input. the input sample starts on the positive edge. reflb (pins 11, 12): channel b low reference. short together and bypass to pins 13, 14 with a 0.1f ceramic chip capacitor as close to the pin as possible. also by- pass to pins 13, 14 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. refhb (pins 13, 14): channel b high reference. short together and bypass to pins 11, 12 with a 0.1f ceramic chip capacitor as close to the pin as possible. also by- pass to pins 11, 12 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. a inb C (pin 15): channel b negative differential analog input. a inb + (pin 16): channel b positive differential analog input. gnd (pins 17, 64): adc power ground. senseb (pin 19): channel b reference programming pin. connecting senseb to v cmb selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to senseb selects an input range of v senseb . 1v is the largest valid input range. v cmb (pin 20): channel b 1.5v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. do not connect to v cma . mux (pin 21): digital output multiplexer control. if mux is high, channel a comes out on da0-da13; channel b comes out on db0-db13. if mux is low, the output bus- ses are swapped and channel a comes out on db0-db13; channel b comes out on da0-da13. to multiplex both channels onto a single output bus, connect mux, clka and clkb together. (this is not recommended at clock frequencies above 80msps.) shdnb (pin 22): channel b shutdown mode selection pin. connecting shdnb to gnd and oeb to gnd results in normal operation with the outputs enabled. connecting shdnb to gnd and oeb to v dd results in normal operation with the outputs at high impedance. connecting shdnb to v dd and oeb to gnd results in nap mode with the outputs at high impedance. connecting shdnb to v dd and oeb to v dd results in sleep mode with the outputs at high impedance. oeb (pin 23): channel b output enable pin. refer to shdnb pin function. db0 C db13 (pins 24 to 30, 33 to 39): channel b digital outputs. db13 is the msb. ognd (pins 31, 50): output driver ground. ov dd (pins 32, 49): positive supply for the output drivers. bypass to ground with 0.1f ceramic chip capacitor. clkout (pin 40): data ready clock output. latch data on the falling edge of clkout. clkout is derived from clkb. tie clka to clkb for simultaneous operation. da0 C da13 (pins 41 to 48, 51 to 56): channel a digital outputs. da13 is the msb. of (pin 57): over? ow/under? ow output. high when an over? ow or under? ow has occurred on either channel a or channel b. oea (pin 58): channel a output enable pin. refer to shdna pin function.
ltc2285 9 2285fb pin functions shdna (pin 59): channel a shutdown mode selection pin. connecting shdna to gnd and oea to gnd results in normal operation with the outputs enabled. connecting shdna to gnd and oea to v dd results in normal operation with the outputs at high impedance. connecting shdna to v dd and oea to gnd results in nap mode with the outputs at high impedance. connecting shdna to v dd and oea to v dd results in sleep mode with the outputs at high impedance. mode (pin 60): output format and clock duty cycle stabilizer selection pin. note that mode controls both channels. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. v cma (pin 61): channel a 1.5v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. do not connect to v cmb . sensea (pin 62): channel a reference programming pin. connecting sensea to v cma selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sensea selects an input range of v sensea . 1v is the largest valid input range. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. functional block diagram figure 1. functional block diagram (only one channel is shown) shift register and correction diff ref amp ref buf 2.2f 1f 1f 0.1f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 2285 f01 input s/h sense v cm a in C a in + 2.2f third pipelined adc stage output drivers control logic shdn of* d13 d0 clkout* *of and clkout are shared between both channels. ? ? ?
ltc2285 10 2285fb timing diagrams dual digital output bus timing (only one channel is shown) multiplexed digital output bus timing t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t c t l n C 4 n C 3 n C 2 n C 1 clka = clkb d0-d13, of 2284 td01 clkout n C 5 n t apb b + 1 b + 2 b + 4 b + 3 b analog input b t apa a + 1 a C 5 b C 5 b C 5 a C 5 a C 4 b C 4 b C 4 a C 4 a C 3 b C 3 b C 3 a C 3 a C 2 b C 2 b C 2 a C 2 a C 1 b C 1 a + 2 a + 4 a + 3 a analog input a t h t d t c t md t l clka = clkb = mux d0a-d13a 2284 td02 clkout d0b-d13b
ltc2285 11 2285fb dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamen- tal input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the ? rst ? ve harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log (v2 2 + v3 2 + v4 2 + ...vn 2 )/v1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the ? fth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are ap- plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are applications information 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodula- tion distortion is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spuri- ous noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches midsupply to the in- stant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) crosstalk crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a C1dbfs signal). converter operation as shown in figure 1, the ltc2285 is a dual cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value ? ve cycles later (see the timing dia- gram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended
ltc2285 12 2285fb applications information with slightly worse harmonic distortion. the clk input is single-ended. the ltc2285 has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h dur- ing this high phase of clk. when clk goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and ? fth stages, resulting in a ? fth stage residue that is sent to the sixth stage adc for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2285 cmos differential sample-and-hold. the analog inputs are con- nected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected figure 2. equivalent input circuit v dd v dd v dd 15 15 c parasitic 1pf c parasitic 1pf c sample 3.5pf c sample 3.5pf ltc2285 a in + a in C clk 2285 f02
ltc2285 13 2285fb applications information from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the ltc2285 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can in? uence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 3.5pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as pos- sible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2285 being driven by an rf trans- former with a center tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the trans- former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 3. single-ended to differential conversion using a transformer 25 25 25 25 0.1f a in + a in C 12pf 2.2f v cm ltc2285 analog input 0.1f t1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 2285 f03
ltc2285 14 2285fb applications information figure 4 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the sfdr at high input frequencies. figure 5 shows a single-ended input circuit. the impedance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun transformer gives better high frequency response than a ? ux coupled center tapped transformer. the coupling capacitors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. figure 4. differential drive with an ampli? er figure 5. single-ended drive figure 6. recommended front end circuit for input frequencies between 70mhz and 170mhz figure 7. recommended front end circuit for input frequencies between 170mhz and 300mhz figure 8. recommended front end circuit for input frequencies above 300mhz 25 25 12pf 2.2f v cm 2285 f04 C C + + cm analog input high speed differential amplifier a in + a in C ltc2285 25 0.1f analog input v cm a in + a in C 1k 12pf 2285 f05 2.2f 1k 25 0.1f ltc2285 25 25 12 12 0.1f a in + a in C 8pf 2.2f v cm analog input 0.1f 0.1f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 2285 f06 ltc2285 25 25 0.1f a in + a in C 2.2f v cm analog input 0.1f 0.1f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 2285 f07 ltc2285 25 25 0.1f a in + a in C 2.2f v cm analog input 0.1f 0.1f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 2285 f08 8.2nh 8.2nh ltc2285
ltc2285 15 2285fb applications information reference operation figure 9 shows the ltc2285 reference circuitry consisting of a 1.5v bandgap reference, a difference ampli? er and switching and control circuit. the internal voltage reference can be con? gured for two pin selectable input ranges of 2v (1v differential) or 1v (0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference ampli? er to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. figure 9. equivalent reference circuit the difference ampli? er generates the high and low reference for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. each adc channel has an independent reference with its own bypass capacitors. the two channels can be used with the same or different input ranges. other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by ap- plying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1f ceramic capacitor. for the best channel matching, connect an external reference to sensea and senseb. figure 10. 1.5v range adc input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise performance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5.7db. see the typical performance characteristics section. driving the clock input the clk inputs can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low jitter squaring circuit before the clk pin (figure 11). v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ? v sense for 0.5v < v sense < 1v 1.5v refl 2.2f 2.2f internal adc high reference buffer 0.1f 2285 f09 4 diff amp 1f 1f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control ltc2285 v cm sense 1.5v 0.75v 2.2f 12k 1f 12k 2285 f10 ltc2285
ltc2285 16 2285fb applications information figure 11. sinusoidal single-ended clk drive figure 12. clk drive using an lvds or pecl to cmos converter figure 13. lvds or pecl clk drive using a transformer the noise performance of the ltc2285 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digi- tizing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, ? lter the clk signal to reduce wideband noise and distortion products generated by the source. it is recommended that clka and clkb are shorted to- gether and driven by the same clock source. if a small time delay is desired between when the two channels sample the analog inputs, clka and clkb can be driven by two different signals. if this delay exceeds 1ns, the performance of the part may degrade. clka and clkb should not be driven by asynchronous signals. figures 12 and 13 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solution. the nature of the received signals also has a large bear- ing on how much snr degradation will be experienced. for high crest factor signals such as wcdma or ofdm, where the nominal power level must be at least 6db to 8db below full scale, the use of these translators will have a lesser impact. the transformer in the example may be terminated with the appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a ca- pacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 ohm series resistor to act as both a low pass ? lter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for re? ections. maximum and minimum conversion rates the maximum conversion rate for the ltc2285 is 125msps. the lower limit of the ltc2285 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on clk 50 0.1f 0.1f 4.7f 1k 1k ferrite bead clean supply sinusoidal clock input 2285 f11 nc7svu04 ltc2285 clk 100 0.1f 4.7f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 2285 f12 ltc2285 clk 5pf-30pf etc1-1t 0.1f v cm ferrite bead differential clock input 2285 f13 ltc2285
ltc2285 17 2285fb applications information small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2285 is 1msps. clock duty cycle stabilizer an optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. using the clock duty cycle stabilizer is recommended for most applications. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits, and the over? ow bit. note that of is high when an over? ow or under? ow has occurred on either channel a or channel b. table 1. output codes vs input voltage a in + C a in C (2v range) of d13 C d0 (offset binary) d13 C d0 (2s complement) >+1.000000v +0.999878v +0.999756v 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122v 0.000000v C0.000122v C0.000244v 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.999878v C1.000000v ltc2285 18 2285fb applications information table 2. mode pin function mode pin output format clock duty cycle stabilizer 0 offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit when of outputs a logic high the converter is either overranged or underranged on channel a or channel b. note that both channels share a common of pin, which is not the case for slower pin compatible parts such as the ltc2284 or ltc2299. of is disabled when channel a is in sleep or nap mode. output clock the adc has a delayed version of the clkb input available as a digital output, clkout. the falling edge of the clkout pin can be used to latch the digital output data. clkout is disabled when channel b is in sleep or nap mode. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe . oe high disables all data outputs including of. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. channels a and b have independent output enable pins ( oea , oeb ). sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels a and b have independent shdn pins (shdna, shdnb). channel a is controlled by shdna and oea , and channel b is controlled by shdnb and oeb . the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode. digital output multiplexer the digital outputs of the ltc2285 can be multiplexed onto a single data bus if the sample rate is 80msps or less. the mux pin is a digital input that swaps the two data busses. if mux is high, channel a comes out on da0-da13; channel b comes out on db0-db13. if mux is low, the output busses are swapped and channel a comes out on db0-db13; channel b comes out on da0-da13. to multiplex both channels onto a single output bus, connect mux, clka and clkb together (see the timing diagram for the multiplexed mode). the multiplexed data is available on either data busthe unused data bus can be disabled with its oe pin. grounding and bypassing the ltc2285 requires a printed circuit board with a clean, unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care
ltc2285 19 2285fb applications information should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2f capacitor be- tween refh and refl can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2285 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2285 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of suf? cient area. clock sources for undersampling undersampling is especially demanding on the clock source, and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not ? lter the clock signal with a narrow band ? lter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a ? lter close to the adc may be bene? cial. this ? lter should be close to the adc to both reduce roundtrip re? ection times, as well as reduce the susceptibility of the traces between the ? lter and the adc. if the circuit is sensitive to close- in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the driver to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing ? ip-? op as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer pcbs. the differential pairs must be close together and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.
ltc2285 20 2285fb applications information evaluation circuit schematic of the ltc2285 c21 0.1f c27 0.1f v dd v dd v dd v dd v dd ov dd v cmb c20 2.2f c18 1f c23 1f c34 0.1f c31 * c17 0.1f c14 0.1f c25 0.1f c28 2.2f c35 0.1f c24 0.1f c36 4.7f e3 v dd 3v e5 pwr gnd v dd ov dd 2285 ai01 c1 0.1f r32 opt r39 1k r1 1k r2 1k r3 1k r10 1k r14 49.9 r20 24.9 r18 * r24 * r17 opt r22 24.9 r23 51 t2 * c29 0.1f c33 0.1f j3 clock input u3 nc7svu04 24 3 5 u4 nc7sv86p5x c15 0.1f c12 4.7f 6.3v l1 bead v dd c19 0.1f c11 0.1f c4 0.1f c2 2.2f c10 2.2f c9 1f c13 1f r15 1k j4 analog input b qdv dd 1 2 3 4 ?? 5 v cmb c8 0.1f c6 * c44 0.1f r6 24.9 r5 * r9 * r4 opt r7 24.9 r8 51 t1 * c3 0.1f c7 0.1f j2 analog input a 1 2 3 5 ?? 4 v cma v cma 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp1 mode r34 4.7k c39 1f v dd ov dd in byp out 15 u12 lt1761es5-byp 3 4 adj c38 0.01f c46 0.1f e4 gnd c45 100f 6.3v opt c40 0.1f c48 0.1f c47 0.1f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e2 ext ref b 12 v dd 34 v cm v dd v cmb 56 ext ref jp3 senseb e1 ext ref a 12 v dd 34 v cm v dd 56 ext ref jp2 sensea c5 0.1f ov dd 3 4 5 6 7 8 9 10 22 21 u2 fxlh42245mpx 20 19 18 17 16 15 14 2 u5 24lc025 a0 a1 a2 a3 v cc wp scl sda 1 2 3 4 8 7 6 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 80 82 84 86 88 90 92 94 96 98 100 79 81 83 85 87 89 91 93 95 97 99 qdv dd v ss scl sda r33 4.7k enable v ccin j1 edge-con-100 r35 100k 1 4 5 3 2 + c41 0.1f qdv dd c52 0.1f c55 0.1f c54 0.1f c53 0.1f r38 4.99k r37 4.99k r36 4.99k scl v ccin v ss sda assembly type dc1098a-a dc1098a-b dc1098a-c dc1098a-d dc1098a-e dc1098a-f u1 ltc2281iup ltc2283iup ltc2285iup ltc2281iup ltc2283iup ltc2285iup r5, r9, r18, r24 24.9 24.9 24.9 12.4 12.4 12.4 c6, c31 12pf 12pf 12pf 8pf 8pf 8pf t1, t2 mabaes0060 mabaes0060 mabaes0060 maba-007159-000000 maba-007159-000000 maba-007159-000000 input frequency 1mhz < a in < 70mhz 1mhz < a in < 70mhz 1mhz < a in < 70mhz 70mhz < a in < 140mhz 70mhz < a in < 140mhz 70mhz < a in < 140mhz *version table msps 125 125 125 125 125 125 bits 10 12 14 10 12 14 a ina + a ina C refha refha refla refla v dd clka clkb v dd reflb reflb refhb refhb a inb C a inb + da7 da6 da5 da4 da3 da2 da1 da0 clkout db13 db12 db11 db10 db9 db8 db7 gnd v dd sensea vcma mode shdna oea of da13 da12 da11 da10 da9 da8 ognd ov dd gnd v dd senseb vcmb mux shdnb oeb db0 db1 db2 db3 db4 db5 db6 ognd ov dd u1 ltc2285 a3 a2 a4 a5 a6 a7 oe a1 a0 b3 b1 b0 124 23 v cca v ccb v ccb ov dd ov dd qdv dd b2 b7 t/ r gnd gnd gnd gnd b5 b4 b6 exposed pad 11 12 13 25 3 4 5 6 7 8 9 10 22 21 u11 fxlh42245mpx 20 19 18 17 16 15 14 2 a3 a2 a4 a5 a6 a7 oe a1 a0 b3 b1 b0 124 23 v cca v ccb v ccb ov dd qdv dd b2 b7 t/ r gnd gnd gnd gnd b5 b4 b6 exposed pad 11 12 13 25 3 4 5 6 7 8 9 10 22 21 u10 fxlh42245mpx 20 19 18 17 16 15 14 2 a3 a2 a4 a5 a6 a7 oe a1 a0 b3 b1 b0 124 23 v cca v ccb v ccb ov dd qdv dd b2 b7 t/ r gnd gnd gnd gnd b5 b4 b6 exposed pad 11 12 13 25 3 4 5 6 7 8 9 10 22 21 u9 fxlh42245mpx 20 19 18 17 16 15 14 2 a3 a2 a4 a5 a6 a7 oe a1 a0 b3 b1 b0 124 23 v cca v ccb v ccb ov dd qdv dd b2 b7 t/ r gnd gnd gnd gnd b5 b4 b6 exposed pad 11 12 13 25 r42 1k gnd c37 10f 6.3v r25 105k r25 105k c51 1f v dd qdv dd in byp out 15 u13 lt1761es5-byp 3 4 adj c49 0.01f gnd c50 10f 6.3v r40 105k r41 100k 2 2
ltc2285 21 2285fb applications information silkscreen top top side
ltc2285 22 2285fb applications information inner layer 2 gnd inner layer 3 power bottom side
ltc2285 23 2285fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 64 63 1 2 bottom view?xposed pad 7.15 0.10 7.15 0.10 7.50 ref (4-sides) 0.75 0.05 r = 0.10 typ r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 7.50 ref (4 sides) 7.15 0.05 7.15 0.05 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35
ltc2285 24 2285fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2006 lt 1207 rev b ? printed in usa typical application part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr ltc1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain ltc1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion: C94db at 1mhz ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.1db snr, 100db sfdr, 64-pin qfn package ltc2220 12-bit, 170msps, 3.3v adc, lvds outputs 890mw, 67.7db snr, 84db sfdr, 64-pin qfn package ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn package ltc2242-12 12-bit, 250msps, 2.5v adc, lvds outputs 740mw, 65.4db snr, 84db sfdr, 64-pin qfn package ltc2254 14-bit, 105msps, 3v adc, lowest power 320mw, 72.4db snr, 88db sfdr, 32-pin qfn package ltc2255 14-bit, 125msps adc, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn package ltc2280 10-bit, dual, 105msps, 3v adc, low crosstalk 320mw, 61.6db snr, 85db sfdr, 64-pin qfn package ltc2282 12-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 70.1db snr, 88db sfdr, 64-pin qfn package ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn package ltc2286 10-bit, dual, 25msps, 3v adc, low crosstalk 150mw, 61.8db snr, 85db sfdr, 64-pin qfn package ltc2287 10-bit, dual, 40msps, 3v adc, low crosstalk 235mw, 61.8db snr, 85db sfdr, 64-pin qfn package ltc2288 10-bit, dual, 65msps, 3v adc, low crosstalk 400mw, 61.8db snr, 85db sfdr, 64-pin qfn package ltc2289 10-bit, dual, 80msps, 3v adc, low crosstalk 422mw, 61.6db snr, 90db sfdr, 64-pin qfn package ltc2290 12-bit, dual, 10msps, 3v adc, low crosstalk 120mw, 71.3db snr, 90db sfdr, 64-pin qfn package ltc2291 12-bit, dual, 25msps, 3v adc, low crosstalk 150mw, 71.4db snr, 90db sfdr, 64-pin qfn package ltc2292 12-bit, dual, 40msps, 3v adc, low crosstalk 235mw, 71.4db snr, 90db sfdr, 64-pin qfn package ltc2293 12-bit, dual, 65msps, 3v adc, low crosstalk 400mw, 71.3db snr, 90db sfdr, 64-pin qfn package ltc2294 12-bit, dual, 80msps, 3v adc, low crosstalk 422mw, 70.6db snr, 90db sfdr, 64-pin qfn package ltc2295 14-bit, dual, 10msps, 3v adc, low crosstalk 120mw, 74.4db snr, 90db sfdr, 64-pin qfn package ltc2296 14-bit, dual, 25msps, 3v adc, low crosstalk 150mw, 74.5db snr, 90db sfdr, 64-pin qfn package ltc2297 14-bit, dual, 40msps, 3v adc, low crosstalk 235mw, 74.4db snr, 90db sfdr, 64-pin qfn package ltc2298 14-bit, dual, 65msps, 3v adc, low crosstalk 400mw, 74.3db snr, 90db sfdr, 64-pin qfn package ltc2299 14-bit, dual, 80msps, 3v adc, low crosstalk 444mw, 73db snr, 90db sfdr, 64-pin qfn package lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 single ended rf and lo ports

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